Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture

Three-Dimensional (3D) integration of circuits based on die and wafer stacking using through-silicon-via is a critical technology in enabling "morethan-Moore", i.e. functional integration of devices beyond pure scaling ("more Moore"). In particular, the scaling from multi-core to many-core architecture is an excellent candidate for such integration. Nevertheless, as much as there are opportunities to explore, designing systems using 3D integration technology has many challenges to tackle. It follows a complex design process involving integration of heterogeneous technologies. It is also expensive to prototype because the 3D industrial ecosystem is not yet complete and ready for low-cost mass production. With trends leading towards 3D many-core architecture, it is also imperative to extend the under-lying Networks-on-Chip (NoC) to efficiently facilitate the communication of such massively integrated cores on a 3D chip. In this thesis scalability and performance issues of NoCs are explored in terms of architecture, organization and functionality of many-core systems. The key contributions of the thesis are made by (1) addressing the challenges in modeling and development of deflection routing NoCs for the use in regular and irregular networks, (2) evaluating new configurations of 3D processor-memory stacking, (3) the use of multi-rate vertical interconnect to optimize network performance, and (4) developing predictive models for performance analysis in many-core architecture. First, we evaluate on-chip network performance in massively integrated many-core architecture. With each addition of cores, the on-chip network size grows and predicting the performance becomes challenging. We propose link and channel models to analyze the network traffic and hence the performance. We consider the absence of a simulation platform for such scalable many-core architecture as a key challenge. We develop a NoC simulation framework to evaluate the performance of a deflection routing network as the architecture scales up to 1000 cores. In designing processor-memory architecture, we propose models and do comparative analysis of proposed 3D processor-memory configurations in scalable many-core architectures. Second, we investigate how the deflection routing NoCs can be designed to maximize the benefit of the fast TSVs as vertical interconnects by clocking them at a rate that is an integer multiple of the clock frequency of the horizontal links. We propose multi-rate models for inter-layer communication. We quantify the performance benefit through cycle-accurate simulations for various configurations of 3D architectures. Finally, the complexity of massively integrated many-core architecture by itself brings a multitude of design challenges such as high-cost of prototyping, increasing complexity of the technology, irregularity of the communication network, and lack of reliable simulation models. In order to reduce the design to market time and lower the cost, we propose average distance models for various traffic patterns to help as analyze such systems. We also formulate a zero-load average distance model that accurately predicts the performance of deflection routing networks in the absence of data flow by capturing the av-